parallel multiplier是什么意思_parallel multiplier的中文翻译

并行乘法器

multiplier───n.[数]乘数；[电子]倍增器；增加者；繁殖者

formula───乘数公式

countercurrent multiplier───逆流倍增器

multiplier circuit───乘法器电路

matrix multiplier───矩阵乘数

multiplier function───乘子函数

multiplier symbols───倍增符号

parallel park───平行停车

DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.───数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。

new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.───提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。

advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.───说明了对偶基比特并行乘法器在硬件规模上的优越性。

A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.───提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。

Design of a parallel multiplier for 16-bit fixed-point DSP───基于16位定点DSP的并行乘法器的设计

By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used RS decoder is constructed.

The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.

The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented.

A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.

DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.───数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。

new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.───提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。

advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.───说明了对偶基比特并行乘法器在硬件规模上的优越性。

A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.───提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。

Design of a parallel multiplier for 16-bit fixed-point DSP───基于16位定点DSP的并行乘法器的设计

By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used RS decoder is constructed.

The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.

The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented.

A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.